TLP - Thread Level Parallelism: UltraSPARC-T1

igor — Thu, 08 Dec 2005 23:02:00 +0000

In my last post I have written a little bit about Thread Level Parallelism and since SUN has officially released its first processor based on TLP I thought this is a good opportunity to write a little something about this nice processor.

Instead of increasing the size of the pipeline by dividing pipeline stages up into smaller units in order to be able to increase the processor tact rate and then fail to keep the pipeline full (as Intel has done it with the P4), SUN did something different. They concentrated on throughput and went away from the classical ILP paradigm.

Their new processor consists of up to 8 cores processing 4 threads per core. So this means that 32 threads can be processed “simultaneously”. Each core can process one instruction every cycle. There is a L1 cache per core and a shared L2 cache. In order to provide the high memory bandwidth necessary to “feed” 32 threads, a crossbar interconnects scheme routes memory references to a banked on-chip level-2 cache that all threads share. All this means more throughput, less energy consumption and more efficient usage of resources.

Are you still reading this post and still interested? Then you should check out this description of the niagara architecture.

ByteLabs: TLP - Thread Level Parallelism: UltraSPARC-T1

TLP - Thread Level Parallelism: UltraSPARC-T1