ByteLabs

The second silicon implementation of an extended EnCore processor is a test-chip codenamed Castle, fabricated in a generic 90nm CMOS process. All of the EnCore test chips are named after hills in Edinburgh; Castle is named after the rock on which Edinburgh Castle is built.

The Castle chip contains an extended version of the EnCore processor, together with a 32KB 4-way set-associative Instruction Cache, and a 32KB 4-way set-associative Data Cache. It is embedded within a system-on-chip (SoC) design that provides a generic 32-bit memory interface, as well as interrupt, clocks and reset signals.

Our paper about Cycle-Accurate Performance Modelling in an Ultra-Fast Just-In-Time Dynamic Binary Translation Instruction Set Simulator got accepted for SAMOS 2010.

Here is the abstract:

“Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-time (JIT) dynamic binary translation (DBT) techniques are able to simulate complex embedded processors at speeds above 500 MIPS. However, these functional ISS do not provide microarchitectural observability. In contrast, low-level cycle-accurate ISS are too slow to simulate full-scale applications, forcing developers to revert to FPGA-based simulations. In this paper we demonstrate that it is possible to run ultra-high speed cycle-accurate instruction set simulations surpassing FPGA-based simulation speeds. We extend the JIT DBT engine of our ISS and augment JIT generated code with a verified cycle-accurate processor model. Our approach can model any microarchitectural configuration, does not rely on prior profiling, instrumentation, or compilation, and works for all binaries targeting a state-of-the-art embedded processor implementing the ARCompact™ instruction set architecture (ISA). We achieve simulation speeds up to 63 MIPS on a standard x86 desktop computer, whilst the average cycle-count deviation is less than 1.5 % for the industry standard EEMBC and CoreMark benchmark suites.“

If you would like to read the joint paper with Tobias and Björn that I am going to present at CGO in Toronto next week, here is the place where you can get it:

Integrated Instruction Selection and Register Allocation for Compact Code Generation Exploiting Freeform Mixing of 16- and 32-bit Instructions

Ivan Lewis, Middle East Minister at the Foreign and Commonwealth Office is coming to the University of Edinburgh to give a ‘lecture’ with the title ‘Why are we in Afghanistan’?

If you read what his speech is about you will soon find out that it is just a lot of war propaganda. Because elections are coming up soon people need to be persuaded of the necessity of war and that is the reason why the UK government is performing what they call a ‘roadshow’ (i.e. propaganda) to ‘inform’ (i.e. mislead) the general public.

Politicians should not abuse our Universities for such purposes and Universities should reject such ‘lectures’. Please come along to the lecture and voice your opinion about this situation.

Here is the official invitation:

“The Rt. Hon. Ivan Lewis, Middle East Minister at the Foreign and Commonwealth Office, is to give a lecture in LT 175 – Law, Old College on Thursday 25th March 2010 at 3.00 p.m. with the title “Why are we in Afghanistan?”.

The lecture will be followed by a Q&A session.

All welcome.

Seating is first-come, first-served.”

See you there…

We came up with another interesting project that might be of interest to you! The full title of this project is “A LLVM Backend for a Just-In-Time Compilation Engine of a state-of-the-art Instruction Set Simulator” and a detailed project specification can be found here.

If you are interested you can either contact me, Björn or Nigel.

Our PaStA research group offers an exciting new project. It is about extending a state-of-the-art high-speed simulator that already implements a JIT compilation engine with a concurrent and adaptive JIT and AOT engine.

The full title is “Concurrent, Adaptive, Just-In-Time and Ahead-Of-Time Compilation in the context of a state-of-the-art Instruction Set Simulator” and a detailed project specification can be found here.

If you are interested you can either contact me or Björn.

Our paper titled ‘Integrated Instruction Selection and Register Allocation for Compact Code Generation Exploiting Freeform Mixing of 16- and 32-bit Instructions’ has been accepted for publication in Proceedings of the International Symposium on Code Generation and Optimization, 2010 (CGO’10). It is a joint paper written together with Tobias Koch and Björn Franke.

The School of Informatics in Edinburgh was hosting this years SICSA DEMOfest'09 where our PASTA research group presented the latest developments sourrounding the next generation EnCore Embedded Microprocessor codenamed Castle.

• More information about DEMOfest'09 event.
• More information about the PASTA Research Group.

As of today the PASTA project has issued an official press release about our new EnCore microprocessor.

Press Release: Gadgets could go greener with high-speed computer chip

I have just finished the facelift of our CArD – Compiler and Architecture Design Group website. The people page gives a good overview about our members and we finally have a news section as well.